1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a gate electrode layer of transistors.
2. Description of the Related Art
Conventionally, polycrystalline silicon has been mainly used as the material of a gate electrode layer of MOS transistors (hereinafter, referred to as MOSFET). This is based on the following reasons. The above polycrystalline silicon stabilizes the interface state between a gate electrode layer and a gate insulating film (gate oxide film) existing under gate electrode layer, and is excellent in mutual adhesion. In addition, impurity elements introduced into the polycrystalline silicon are properly selected, and thereby, in N-type and P-type MOSFETs, it is possible to form a gate electrode layer having the optimal work function, and to control threshold voltage values.
However, with the development of micro-fabrication in MOSFET, depletion in the gate electrode layer must be considered as a serious problem incapable of disregarding. More specifically, the above depletion of the gate electrode layer is that when voltage is applied to the gate electrode layer, a depletion layer is formed at a gate electrode layer region near to the interface between the gate electrode layer and the gate insulating film.
The cause of the depletion of the gate electrode layer arises from the reason why a polycrystalline silicon film is used as the material of semiconductors. In N-type and P-type MOSFETs, the polycrystalline silicon film functions as the gate electrode layer. In this case, in order to fulfill the above function, impurity elements must be introduced into the polycrystalline silicon film, using ion implantation technique. However, there exists the upper limit in the concentration of impurities such as donor or acceptor introduced into the polycrystalline silicon film. From the above reasons, it can be seen that it is difficult to eliminate the depletion of the gate electrode layer when forming the gate electrode layer using the polycrystalline silicon film. On the contrary, metals are used as the material of the gate electrode layer, what is called, the technical development of MOSFET including a metal gate electrode layer has been made. In such MOSFET, the entirety of the gate electrode layer or the gate electrode layer interface contacting with the gate insulating film is formed of refractory metal materials, i.e., metal materials having a high melting-point. By doing so, it is possible to eliminate the depletion of the gate electrode layer.
If the gate electrode layer is formed using dry etching technique, it may be formed in the following manner. The principal portion of the gate electrode layer is formed of the polycrystalline silicon film; on the other hand, the gate electrode layer interface contacting with the gate insulating film is formed of refractory metal materials. In this case, the polycrystalline silicon film can be readily and accurately formed into a gate electrode layer pattern using the conventional dry etching technique.
The manufacturing process of semiconductor devices according to the conventional technique will be described below with reference to FIG. 6 to FIG. 8. Here, the method of manufacturing CMOS transistors will be described as one example.
FIGS. 6A to 6C, FIGS. 7A to 7C and FIGS. 8A to 8C are cross-sectional views in a direction vertical to the lengthwise direction of the gate electrode layer in N-type and P-type MOSFETs.
As shown in FIG. 6A, a shallow trench isolation region 201 is formed on a silicon substrate 200 with a predetermined interval using known STI (Shallow Trench Isolation) technique. Thereafter, an aluminum oxide film (Al2O3 film) 202 and a titanium nitride film 203 are successively formed.
Each interval between the isolation regions 201 is used as a device forming region where a semiconductor device such as N-type or P-type MOS transistor is formed. In the present example, as seen from FIG. 6A, the left side is an N-type MOSFET region; on the other hand, the right side is a P-type MOSFET region.
The aluminum oxide film (Al2O3 film) 202 is used as the material for forming the gate insulating film of the N-type and P-type MOSFETs so as to have a thickness of about 2 nm. In addition, the refractory metal material, that is, the titanium nitride film 203 is used as part of the gate electrode layer so as to have a thickness of about 10 nm.
As depicted in FIG. 6B, a photo resist film 204 is formed so as to cover the N-type MOSFET region using lithography technique. Thereafter, wet etching is carried out using the photo resist film 204 as a mask so that the titanium nitride film 203 existing on the P-type MOSFET region can be removed. In this case, hydrogen peroxide water (H2O2) is used for the wet etching process so that the titanium nitride film 203 existing on the P-type MOSFET region can be removed.
As described above, the titanium nitride film 203 existing on the P-type MOSFET region is removed by the above wet etching process. Thereafter, the aluminum oxide film (Al2O3) 202 (gate insulating film) on the P-type MOSFET region is directly exposed to a processing solution, and then, the surface is non-uniformly etched by the processing solution. For this reason, flatness reduces in the surface of the aluminum oxide film (Al2O3) 202; as a result, reliability as gate insulating film also reduces.
A mixed solution of sulfuric acid and hydrogen peroxide water is used so that the photo resist film 204 can be removed. Thereafter, as illustrated in FIG. 6C, a tungsten nitride film 205 is formed as a refractory metal film on the N-type and P-type MOSFET regions so as to have a thickness of about 10 nm. Next, a polycrystalline silicon film 206 is formed over the entire surface of the above tungsten film by CND process. In this case, the polycrystalline silicon film 206 is formed in a state of containing impurities such as phosphorus (P).
In the N-type MOSFET region, the tungsten nitride film 205 is formed on the titanium nitride film 203 in the multi-layer form. In the P-type MOSFET region, the tungsten nitride film 205 is used as the material for forming a metal gate layer.
Heat treatment (anneal process) of about 800xc2x0 C. is carried out so that impurities (e.g., phosphorus (P)) contained in the polycrystalline silicon film 206 can be activated. Thereafter, as shown in FIG. 7A to FIG. 7C, a gate electrode layer pattern will be formed on each of the N-type and P-type MOSFET regions using lithography and dry etching techniques.
First, as illustrated in FIG. 7A, in each of the N-type and P-type MOSFET regions, a gate electrode layer pattern is formed on polycrystalline silicon film 206 using a photo resist pattern 207 as a mask. More specifically, in each of the N-type and P-type MOSFET regions, the photo resist pattern 207 having a dimension and shape of the gate electrode layer is simultaneously formed on the polycrystalline silicon film 206 using lithography techniques. Thereafter, the photo resist film 207 is used as a mask, and then, a gate electrode layer pattern is transferred to the polycrystalline silicon film 206 using dry etching technique such as reactive ion etching (hereinafter, referred to as RIE).
As seen from FIG. 7B, in each of the N-type and P-type MOSFET regions, with the use of the polycrystalline silicon film 206, the tungsten nitride film 205 is simultaneously etched into a predetermined dimension and shape using dry etching technique. In this case, RIE process is employed as the dry etching technique.
As shown in FIG. 7C, in the N-type MOSFET region, with the use of a multi-layer pattern of the polycrystalline silicon film 206 and the tungsten nitride film 205 as a mask, the titanium nitride film 203 is etched into a predetermined dimension and shape using dry etching technique. In this case, RIE process is employed as the dry etching technique.
In the above manner, a multi-layer gate electrode layer 208 (polycrystalline silicon film 206/tungsten nitride film 205/titanium nitride film 203) is formed in the N-type MOSFET region. Likewise, a multi-layer gate electrode layer 209 (polycrystalline silicon film 206/tungsten nitride film 205) is formed in the P-type MOSFET region.
Thereafter, as depicted in FIG. 8A to FIG. 8C, source and drain regions will be formed in each of the N-type and P-type MOSFET regions using the above gate electrode layers 208 and 209 as a mask. The following is a detailed description on the formation of the source and drain regions.
As illustrated in FIG. 8A, in the N-type and P-type MOSFET regions, N-type shallow junction regions 210a, 210b and P-type shallow junction regions 211a, 211b are formed at the positions of the source and drain regions.
First, in the N-type MOSFET region, impurities are introduced using the gate electrode layer 208 as a mask, and thereafter, N-type shallow junction regions 210a and 210b are formed at the positions of the source and drain regions. In this case, although is not specially illustrated, in the N-type MOSFET region, phosphorus (P) or arsenic (As) is introduced into source and drain shallow regions at a predetermined concentration (dosage) using ion implantation technique.
Likewise, in the P-type MOSFET region, impurities are introduced using the gate electrode layer 209 as a mask, and thereafter, P-type shallow junction regions 211a and 211b are formed at the positions of the source and drain regions. In this case, although is not specially illustrated, in the P-type MOSFET region, boron (B) is introduced into the shallow position of the source and drain shallow regions at a predetermined concentration (dosage) using ion implantation technique.
Thereafter, heat treatment (anneal process) is carried out so that impurities of the above N-type shallow junction regions 210a; 210b and P-type shallow junction regions 211a; 211b can be activated.
As seen from FIG. 8B, in the N-type MOSFET region, using the gate electrode layer 208 and a gate sidewall insulation film 212 as a mask, N-type deep junction regions 214a and 214b are formed at the positions of the source and drain regions. Likewise, in the P-type MOSFET region, using the gate electrode layer 209 and a gate sidewall insulation film 213 as a mask, P-type deep junction regions 215a and 215b are formed at the positions of the source and drain regions.
In this case, using a silicon nitride film, gate sidewall insulation films 212 and 213 are formed along each sidewall of the gate electrode layers 208 and 209. Thereafter, in the N-type MOSFET region, using the gate electrode layer 208 and the gate sidewall insulation film 212 as a mask, impurities are introduced so that the above N-type deep junction regions 214a and 214b can be formed at the positions of the source and drain regions. In this case, although is not specially illustrated, in the N-type MOSFET region, phosphorus (P) or arsenic (As) is introduced into deep positions of the source and drain regions at a predetermined concentration (dosage) using ion implantation technique.
Likewise, in the P-type MOSFET region, using the gate electrode layer 209 and the gate sidewall insulation film 213 as a mask, impurities are introduced so that the above P-type deep junction regions 215a and 215b can be formed at the positions of the source and drain regions. In this case, although is not specially illustrated, in the P-type MOSFET region, boron (B) is introduced into deep positions of the source and drain regions at a predetermined concentration (dosage) using ion implantation technique.
Thereafter, heat treatment (anneal process) is carried out so that impurities of the above N-type deep junction regions 214a; 214b and P-type deep junction regions 215a; 215b can be activated.
In the process of forming the gate sidewall insulation films 212 and 213, the aluminum oxide film (gate insulating film) 202 existing on the source and drain regions are removed by etching so that an opening can be formed. By doing so, electric connection with conductive materials is made.
As shown in FIG. 8C, in the N-type MOSFET region, a cobalt silicide (CoSi) layer 216 is formed on the gate electrode layer 208 and the surface layer of the source and drain regions (N-type deep junction regions 214a; 214b) using salicide technique. Likewise, in the P-type MOSFET region, a cobalt silicide (CoSi) layer 217 is formed on the gate electrode layer 209 and the surface layer of the source and drain regions (P-type deep junction regions 215a; 215b). In this manner, the FET structure of CMOS transistors can be completed.
Here, in the N-type MOSFET region, the gate electrode layer is provided with the titanium nitride film as the metal gate layer. On the other hand, in the P-type MOSFET region, the gate electrode layer is provided with the tungsten nitride film as the metal gate layer. As described above, according to the conventional technique, in the N-type and P-type MOSFET regions, different materials selected from refractory metals and refractory metal nitrides are mainly used. This is because the work function value of materials for forming the metal gate layer is considered so that the difference between threshold voltages is given.
According to the conventional method of manufacturing semiconductor devices, in the gate electrode layer, it is easy to partially process the polycrystalline silicon film using the above-mentioned dry etching technique. However, in the process of etching materials of the metal gate layer (titanium nitride film 203, tungsten nitride film 205) such as refractory metal materials and refractory nitride films, the following problems arise.
That is, as seen from FIG. 8C, in the N-type MOSFET region, the gate electrode layer 208 is formed into the multi-layer film comprising the polycrystalline silicon film 206, tungsten nitride film 205 and titanium nitride film 203. On the other hand, in the P-type MOSFET region, the gate electrode layer 209 is formed into the multi-layer film comprising the polycrystalline silicon film 206 and the tungsten nitride film 205. Thus, the gate electrode layer structure differs in the N-type and P-type MOSFET regions; for this reason, it is difficult to simultaneously process and form each gate electrode layer in both regions by dry etching technique.
In such a case, particularly, when forming MOSFETs having different threshold voltage in each region based on circuit design conditions, the manufacturing process becomes complicate in accordance with the kind of the threshold voltages. As a result, this is a factor of reducing efficiency in production process.
In addition, in the N-type MOSFET region, it is difficult to accurately etch the titanium nitride film 203 in a state of keeping sufficient etching selectivity between the aluminum oxide film (Al2O3) 202 forming the gate insulating film and the titanium nitride film 203. In the N-type MOSFET region, the same problem as above arises between the tungsten nitride film 205 and the aluminum oxide film 202 forming the gate insulating film. This is a factor of reducing processing accuracy in each gate electrode layer and the gate insulating film.
With the conventional method of manufacturing semiconductor devices, it is possible to readily and accurately etch part of polycrystalline silicon. However, as described before, in the process of forming the metal gate layers (refractory metal, refractory nitride films, etc.), there is a problem that etching accuracy reduces and efficiency in production process is hindered. In particular, when forming MOSFETs having different threshold voltage in each region in accordance with circuit design conditions, the manufacturing process becomes complicate, and also, processing accuracy reduces.
According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode layer formed on the gate insulating film; source and drain regions formed at both sides of the gate electrode layer; and a channel region between the source and drain regions, wherein the gate electrode layer comprises a polycrystalline silicon layer and a metal layer formed between the gate insulating film and the polycrystalline silicon layer, and the metal layer has an electron density of 1.0xc3x971021 atoms/cm3 or more.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a gate insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the gate insulating film; introducing a metal material into a predetermined region of the polycrystalline silicon film at an amount of the solid soluble limit or more; etching the polycrystalline silicon film to form, on the gate insulating film, a polycrystalline silicon gate layer to which the metal material is introduced, the polycrystalline silicon gate layer forming part of a gate electrode layer; forming source and drain regions at both sides of the polycrystalline silicon gate layer; and performing heat treatment to separate the metal material from the polycrystalline silicon gate layer to form a metal material segregation layer by the segregated metal material between the gate insulating film and the polycrystalline silicon gate layer.
According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a gate insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the gate insulating film; introducing a first metal material into a first region of the polycrystalline silicon film at an amount of the solid soluble limit or more; introducing a second metal material into a second region of the polycrystalline silicon film at an amount of the solid soluble limit or more; etching the polycrystalline silicon film to form, on the gate insulating film, a first polycrystalline silicon gate layer to which the first metal material is introduced and a second polycrystalline silicon gate layer to which the second metal material is introduced, the first polycrystalline silicon gate layer forming part of a first gate electrode layer and the second polycrystalline silicon gate layer forming part of a second gate electrode layer; forming source and drain regions at both sides of each of the first and second polycrystalline silicon gate layers; and performing heat treatment to separate the first metal material from the first polycrystalline silicon gate layer to form a first segregation layer by the segregated first metal material between the gate insulating film and the first polycrystalline silicon gate layer and separate the second metal material from the second polycrystalline silicon gate layer to form a second segregation layer by the segregated second metal material between the gate insulating film and the second polycrystalline silicon gate layer.